PIC18F258-ESLASHSOSQTP datasheet(43/402 Pages) MICROCHIP

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DS41159E-page 41

PIC18FXX8

4.5

Clocking Scheme/Instruction

Cycle

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the

Program Counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The instruc-

tion is decoded and executed during the following Q1

through Q4. The clocks and instruction execution flow

are shown in Figure 4-4.

FIGURE 4-4:

CLOCK/INSTRUCTION CYCLE

4.6

Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute take another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO),

two cycles are required to complete the instruction

(Example 4-2).

A fetch cycle begins with the Program Counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register” (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

4.7

Instructions in Program Memory

The program memory is addressed in bytes. Instruc-

tions are stored as two bytes or four bytes in program

memory. The Least Significant Byte of an instruction

word is always stored in a program memory location

with an even address (LSB = 0). Figure 4-3 shows an

example of how instruction words are stored in the

program memory. To maintain alignment with instruc-

tion boundaries, the PC increments in steps of 2 and

the LSB will always read ‘0’ (see Section 4.4 “PCL,

PCLATH and PCLATU”).

The CALL and GOTO instructions have an absolute

program memory address embedded into the instruc-

tion. Since instructions are always stored on word

boundaries, the data contained in the instruction is a

word address. The word address is written to PC<20:1>,

which accesses the desired byte address in program

memory. Instruction #2 in Example 4-3 shows how the

instruction “GOTO 000006h” is encoded in the program

memory. Program branch instructions that encode a

relative address offset operate in the same manner. The

offset value stored in a branch instruction represents the

number of single-word instructions by which the PC will

be offset. Section 25.0 “Instruction Set Summary”

provides further details of the instruction set.

OSC1

OSC2/CLKO

(RC Mode)

PC + 2

PC + 4

Fetch INST (PC)

Execute INST (PC – 2)

Fetch INST (PC + 2)

Execute INST (PC)

Fetch INST (PC + 4)

Execute INST (PC + 2)

Internal

Phase

Clock

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