PIC18F258-ESLASHSOSQTP datasheet(158/402 Pages) MICROCHIP

158 / 402 page

PIC18FXX8

DS41159E-page 156

17.4.2

OPERATION

The MSSP module functions are enabled by setting

MSSP Enable bit, SSPEN (SSPCON1<5>).

The SSPCON1 register allows control of the I2C

operation. Four mode selection bits (SSPCON1<3:0>)

allow one of the following I2C modes to be selected:

•I2C Master mode, clock = OSC/4 (SSPADD +1)

•I2C Slave mode (7-bit address)

•I2C Slave mode (10-bit address)

•I2C Slave mode (7-bit address) with Start and

Stop bit interrupts enabled

•I2C Slave mode (10-bit address) with Start and

Stop bit interrupts enabled

•I2C Firmware Controlled Master mode, slave is

Idle

Selection of any I2C mode with the SSPEN bit set

forces the SCL and SDA pins to be open-drain, pro-

vided these pins are programmed to inputs by setting

the appropriate TRISC bits. To ensure proper operation

of the module, pull-up resistors must be provided

externally to the SCL and SDA pins.

17.4.3

SLAVE MODE

In Slave mode, the SCL and SDA pins must be config-

ured as inputs (TRISC<4:3> set). The MSSP module

will override the input state with the output data when

required (slave-transmitter).

The I2C Slave mode hardware will always generate an

interrupt on an address match. Through the mode

select bits, the user can also choose to interrupt on

Start and Stop bits.

When an address is matched, or the data transfer after

an address match is received, the hardware automati-

cally will generate the Acknowledge (ACK) pulse and

load the SSPBUF register with the received value

currently in the SSPSR register.

Any combination of the following conditions will cause

the MSSP module not to give this ACK pulse:

• The Buffer Full bit, BF (SSPSTAT<0>), was set

before the transfer was received.

• The overflow bit, SSPOV (SSPCON1<6>), was

set before the transfer was received.

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The

BF bit is cleared by reading the SSPBUF register, while

bit SSPOV is cleared through software.

The SCL clock input must have a minimum high and

low for proper operation. The high and low times of the

I2C specification, as well as the requirement of the

MSSP module, are shown in timing parameter #100

and parameter #101.

17.4.3.1

Addressing

Once the MSSP module has been enabled, it waits for

a Start condition to occur. Following the Start condition,

the 8 bits are shifted into the SSPSR register. All incom-

ing bits are sampled with the rising edge of the clock

(SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match and the BF

and SSPOV bits are clear, the following events occur:

The SSPSR register value is loaded into the

SSPBUF register.

The Buffer Full bit BF is set.

An ACK pulse is generated.

MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is

set (interrupt is generated if enabled) on the

falling edge of the ninth SCL pulse.

In 10-bit Address mode, two address bytes need to be

received by the slave. The five Most Significant bits

(MSbs) of the first address byte specify if this is a 10-bit

address. Bit R/W (SSPSTAT<2>) must specify a write so

the slave device will receive the second address byte.

For a 10-bit address, the first byte would equal

‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs

of the address. The sequence of events for 10-bit

address is as follows, with steps 7 through 9 for the

slave-transmitter:

Receive first (high) byte of address (bits SSPIF,

BF and bit UA (SSPSTAT<1>) are set).

Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

Receive second (low) byte of address (bits

SSPIF, BF and UA are set).

Update the SSPADD register with the first (high)

byte of address. If match releases SCL line, this

will clear bit UA.

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

Receive Repeated Start condition.

Receive first (high) byte of address (bits SSPIF

and BF are set).

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

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