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ICS1893CFILF 数据表(PDF) 103 Page - Integrated Circuit Systems |
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ICS1893CFILF 数据表(HTML) 103 Page - Integrated Circuit Systems |
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103 / 126 page ![]() Chapter 9 DC and AC Operating Conditions ICS1893CF, Rev. F, 03/01/07 Mar. 2007 103 ICS1893CF Data Sheet Rev. F - Release Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 9.5 Timing Diagrams 9.5.1 Timing for Clock Reference In (REF_IN) Pin Table 9-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. Figure 9-2 shows the timing diagram for the time periods. Note: The REF_IN switching point is 50% of VDD. Figure 9-2. REF_IN Timing Diagram Table 9-8. REF_IN Timing Time Period Parameter Conditions Min. Typ. Max. Units t1 REF_IN Duty Cycle – 45 50 55 % t2 REF_IN Period – – 40 – ns REF_IN t1 t2 |
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