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ICS1893CFILF 数据表(PDF) 105 Page - Integrated Circuit Systems

部件名 ICS1893CFILF
功能描述  3.3-V 10Base-T/100Base-TX Integrated PHYceive
PDF  126 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS1893CFILF 数据表(HTML) 105 Page - Integrated Circuit Systems

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Chapter 9 DC and AC Operating Conditions
ICS1893CF, Rev. F, 03/01/07
Mar. 2007
105
ICS1893CF Data Sheet Rev. F - Release
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
9.5.3 Timing for Receive Clock (RXCLK) Pins
Table 9-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various
interfaces. Figure 9-4 shows the timing diagram for the time periods.
Figure 9-4. Receive Clock Timing Diagram
Table 9-10. MII Receive Clock Timing
Time
Period
Parameter
Conditions
Min. Typ. Max. Units
t1
RXCLK Duty Cycle
–
35
50
65
%
t2a
RXCLK Period
100M MII (100Base-TX)
–
40
–
ns
t2b
RXCLK Period
10M MII (10Base-T)
–
400
–
ns
RXCLK
t1
t2



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