2

Tightly Coupled Memories (TCMs)

Two optional TCMs private to each core: an ITCM for instructions and

literal pool data and a DTCM for data.

Debug

Armv8-R AArch64 debug logic with debug over power-down support.

Cross Trigger Interface (CTI) for multiprocessor debugging.

Optional support for integrating CoreSight Embedded Logic Analyzer,

ELA-600 for advanced debug capability and signal observability.

Performance Monitors Extension support for software profiling and

performance debugging based on the PMUv3 architecture.

Memory Built-In Self-Test (MBIST) for testing memories at boot time.

Trace

Embedded Trace Macrocell (ETM), compliant with ETMv4.5, for

instruction and data trace.

Memory Protection Unit (MPU)

Two programmable MPUs controlled from EL1 and EL2 respectively, for

determining the attributes for each memory location including

permissions, type, and cacheability.

Memory Management Unit (MMU)

Fine-grained memory system control through virtual-to-physical address

mappings and memory attributes held in translation tables.

About the Cortex-R82 Processor

The Cortex-R82 processor is a high-performance, high-efficiency, multi-core, in-order,

superscalar processor for use in real-time embedded applications. The Cortex-R82

processor implements the Armv8-R AArch64 architecture.

Interfaces supported by the processor include:

AMBA 5 AXI

AMBA 4 AXI4-Stream

AMBA 4 APB

AMBA 4 ATB

AMBA CHI

Instruction ATB trace

Data ATB trace

AMBA ACE5-Lite

Q-channel

P-channel

CTI