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The Cortex-R82 processor has:

A shared Main Master (MM) port implemented as AXI5 256-bit providing access for

instructions, data, and peripherals. This interface can optionally be a 256-bit

CHI-E interface.

An optional AXI5 256-bit shared Low-latency RAM (LLRAM) port providing

low-latency access for instructions, data, and peripherals. (Optional here means that

the logic is always present, but it can be disabled.)

An ACE5-Lite 128-bit shared slave main Accelerator Coherency Port (ACP) for

external access to MM address ranges. ACP enables I/O coherency for external

agents with the per-core L1 data cache and shared L2 cache.

An optional AXI5 64-bit Shared Peripheral Port (SPP) for providing access to

peripherals. (Optional here means that the logic is always present,

but it can be disabled.)

A 128-bit shared AXI-S port used for two purposes:

-

As an LLRAM Accelerator Coherency Port enabling I/O coherent external

access to the LLRAM port.

-

As a TCM slave enabling external agents to access the TCMs

within the cores.

An optional, shared, and unified 8-way L2 cache. The L2 cache can cache instructions

and data only from the MM port but not the LLRAM port. The L2 memory supports

cache maintenance operations according to the Arm architecture and memory

testing using MBIST.

64-byte cache lines for the L2 cache.

RAM testing using MBIST.

Each core within the Cortex-R82 processor has:

An optional AXI5 32-bit Low-latency Peripheral Port (LLPP) for providing

access to peripherals. (Optional here means that the logic is always present, but it

can be disabled.)

An optional Instruction Tightly Coupled Memory (ITCM) with configurable

size 0 Or from 16KB to 1MB in powers of 2. ITCM provides lowest-latency access

for instructions and data. (Optional here means that the logic is always present, but

the size can be 0.) ITCM is unified, that is, although it is optimized for instruction use,

it is also available for data. Optional wait-states are supported.

An optional Data Tightly Coupled Memory (DTCM) with configurable size 0 or from

16KB to 1MB in powers of 2. DTCM provides lowest-latency access for data only.

(Optional here means that the logic is always present, but the size can be 0.)