4

Cortex-R82 Components

The Cortex-R82 processor system includes two top-level modules:

The Cortex-R82 processor

The DebugBlock

The DebugBlock is separated from the Cortex-R82 processor to allow the implementation of

the debug components in an always-on power domain, enabling debug over power-down.

Power Policy Units

The Cortex-R82 processor includes one Power Policy Unit (PPU) per core and one PPU for

the processor cluster that control power modes and resets. The PPUs can be programmed to

directly select a specific power mode or to autonomously switch between power modes within

a specified range, based on the requirements of the processor. The PPUs can be programmed

using the Utility bus, either by a System Control Processor (SCP) or by the Cortex-R82

processor (through a loopback connection).

Shared Bridge

The Shared Bridge (SB) decouples the DebugBlock and other components in the system from

the CPU bridge in each core. The SB includes clock and power control logic for the cluster and

interacts with the L2 coherency logic for SCLK clock gating.

L2 coherency logic

The L2 coherency logic maintains coherency between all the cores and caches within the

cluster for the Main Master (MM) port accesses. It contains buffers that can handle direct

cache-to-cache transfers between cores without having to read or write data to the L2

cache. Cache-line migration enables dirty cache lines to be moved between cores. There is no

requirement to write back transferred cache-line data to the L2 cache.

CPU bridges

The CPU bridges control buffering between the cores within the Cortex-R82 processor.

Clock and power management

The cluster supports a set of power-saving modes that are controlled by an external power

controller. The modes are selected through power-mode requests on P-Channels, for each of

the cores, and a separate P-Channel for the Cortex-R82 processor. Clock gating is supported

through Q-Channel requests from an external clock controller to the Cortex-R82 processor.

The Q-Channels allow individual control of the SCLK, PCLK, and ATCLK clock inputs.