7

Direct Memory Access (DMA) to all the TCMs in all cores via a TCM Slave port

implemented through AXI-S. Optional wait-states are supported.

4-way L1 instruction cache with configurable size from 16KB to 64KB in powers of

two that can cache instructions from the MM port or the LLRAM port.

4-way L1 data cache with configurable size from 16KB to 64KB in powers of

two that can cache data with Write-Through caching for LLRAM locations and

Write-Back caching for MM locations.

64-byte cache lines for both L1 instruction and L1 data caches.

A Store buffer Unit (STU) for merging and forwarding (as appropriate) stores to

TCMs (ITCM and DTCM), L1 caches, LLPP, SPP, LLRAM, and MM.

128-bit data path for loads and stores to caches and TCMs (ITCM and DTCM).

Cache maintenance operations according to Arm architecture.

RAM testing using MBIST.

Optional Error Correcting Code (ECC) protection for all functional RAMs providing

Single Error Correct Double Error Detect (SECDED) scheme if there is a need to

produce corrected data from error data or Double Error Detect (DED)

scheme otherwise.

Memory Management Unit

The Memory Management Unit (MMU) implements the Virtual Memory System Architecture

(VMSA) and is responsible for:

Controlling the translation table walk hardware that accesses translation tables in

main memory.

Translating Virtual Addresses (VAs) to Physical Addresses (PAs).

Providing fine-grained memory system control through a set of virtual-to-physical

address mappings and memory attributes that are held in translation tables.

Each stage of address translation uses a set of address translations and associated memory

properties that are held in translation tables. Translation table entries can be cached into a

Translation Lookaside Buffer (TLB).

The MMU includes the following components:

15-entry, fully associative L1 instruction TLB.

16-entry, fully associative L1 data TLB.

1024-entry L2 TLB (256 sets of 4 ways).

32-entry walk cache (8 sets of 4 ways).