CORTEX-R82 datasheet(11/13 Pages) ARM

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AXI-S

AMBA ACE5-Lite

128-bit

Enables external agents

to access to the TCMs and

LLRAM port.

WFE event

signaling

Signals for Wait-For-Event

(WFE) wake-up events.

Clock state control

Q-Channel

Q-Channels for clock gating

control.

Power state control

P-Channel

P-Channels for

Cortex-R82 processor

power management.

Main Accelerator

Coherency Port

(ACP)

AMBA 5 ACE-Lite

128-bit

Provide access to the MM

port to external masters.

Shared Peripheral

Port (SPP)

AMBA 5 AXI

64-bit

Optional shared SPP for

minimum latency access to

memory and devices.

Main Master (MM)

AMBA 5 AXI or CHI

256-bit

Shared MM port for accesses

to high-latency memory and

non-critical peripherals.

Generic Timer

Input for the Generic Timer

counter value. The counter

value is distributed to all

cores. Each core outputs

timer events.

Design for Test

(DFT)

Interface to support access

for Automatic Test Pattern

Generation (ATPG) scan-path

testing.

DebugBlock Interfaces

Name

Protocol

Details

External debug

AMBA 4 APB

Slave interface to external debug

component, for example a Debug Access

Port (DAP). Allows access to Debug

registers and resources.

DebugBlock

AMBA 4 APB

APB interface between the Cortex-R82

processor and the DebugBlock.

Cross-trigger channel interface

CTI

Allows cross-triggering to be extended

to external SoC components.

Power management

Q-Channel

Enables communication to an external

power controller to control clock gating

and power-down.

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