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The Cortex-R82 processor implements an EL1-MMU for EL0 and EL1 memory accesses. This

MMU is optional and configurable on a per-core basis. Each Cortex-R82 core supports having

both an EL1-MPU and EL1-MMU and software can choose which one to use. However, if no

EL1-MPU is present, then an EL1-MMU must be present.

Memory Protection Unit

The Memory Protection Unit (MPU) implements the Protected Memory System Architecture

(PMSA) and determines the attributes for each memory location including permissions, type,

and cacheability.

Access permissions determine which levels of privilege are permitted to access a location and

whether write access or instruction execution are permitted. Memory type and cacheability

affect how the Cortex-R82 processor handles particular accesses, for example, if the

processor permits two stores to be merged into a single write access.

The Cortex-R82 processor implements two programmable MPUs, EL1-MPU and EL2-MPU,

controlled from EL1 and EL2 respectively. These MPUs are optional and configurable on a

per-core basis. Each Cortex-R82 core supports having both an EL1-MPU and EL1-MMU and

software can choose which one to use. However, if no EL1-MMU is present, then an EL1-MPU

must be present. The EL2-MPU is optional but is required if virtualization at EL2 is to be used.

Debug and trace components

The Cortex-R82 processor supports a range of debug, test, and trace options including:

Per-core PMU to monitor events that happen within the core. Provides six

performance event counters and one cycle counter.

Per-core debug logic providing six hardware breakpoints and four watchpoints.

Per-core ETM instruction and data trace on separate ATB buses:

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An ATB4 32-bit bus for instruction.

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An ATB4 128-bit bus for data and ELA.

The trace is generated per core, but the ATB buses are shared between the cores.

Support for a cluster level CoreSight ELA-600 Embedded Logic Analyzer to monitor

the hardware signals related to the shared logic.