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Arm Cortex-R82 Processor Datasheet

Datasheet

Overview

The Cortex-R82 processor is the first Armv8-R 64-bit processor and enables the higher

compute performance needed for the next generation of data storage and to run new

workloads, such as machine learning (ML). It is Arm’s first Cortex-R processor to support

a trusted and robust ecosystem of rich operating systems and software components that

already exist in the Linux and cloud development ecosystem.

Features

Feature

Description

Architecture

Armv8-

R, AArch64 architecture, A64 instruction set.

Compliant with Armv8.4-A extensions.

Pipeline

Eight-stage, in-order, superscalar pipeline with direct and indirect

branch prediction.

Bus Architecture

AMBA 5 AXI and ACE protocol.

AMBA 4 AXI4-Stream protocol for interrupts.

AMBA 4 APB protocol for debug.

AMBA 4 ATB protocol for debug.

AMBA CHI protocol.

Security

Secure state operation only at all Exception levels (EL0 to EL2).

Compatible with Arm TrustZone technology.

Cache Protection

Reliability, Availability, and Serviceability (RAS) Extension.

Optional Error Correcting Code (ECC), Single Error Correct Double Error

Detect (SECDED) or Double Error Detect (DED) protection for all of the

instantiated caches, cache tag and data RAMs and the TCM RAMs.

Generic Interrupt Controller (GIC)

GIC CPU interface to connect to an external GICv3.2

interrupt distributor.

Generic Timer

Generic Timer interface supporting 64-bit count input from an external

system counter.

Floating Point

Optional Half Precision (HP), Single Precision (SP) and Double Precision

(DP) floating-point architecture support, and Advanced Single Instruction

Multiple Data (SIMD), also known as Neon technology.

L1 Cache

Separate L1 data cache and L1 instruction cache private to each core.

L2 Cache

An optional, shared (between all cores), and unified (instructions and

data) L2 cache.

Partial L2 cache power-down support.

Figure 1:

Block diagram of the Cortex-R82 processor