ST10F272M datasheet(128/175 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F272M

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Stand-by supply current(12)

(RTC on, 32 kHz Oscillator on,

main VDD off, VSTBY on)

ISB2

–

120

µA

VSTBY = 5.5V

TA = TJ = 25°C

–

500

µA

VSTBY = 5.5V

TA = TJ = 125°C

Stand-by supply current(1)(12)

(VDD transient condition)

ISB3

–2.5

–

Not 100% tested, guaranteed by design characterization.

This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float

and the voltage is imposed by the external circuitry.

Port 5 leakage values are granted for not selected A/D Converter channel. One channels is always selected (by default,

after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.

The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes)

implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits:

failures in Flash reading may occur (sense amplifier perturbation). Refer to next Figure 37 for a scheme of the input

circuitry.

Overload conditions occur if the standard operating conditions are exceeded, that is, the voltage on any pin exceeds the

specified range (that is, VOV > VDD + 0.3V or VOV < -0.3V). The absolute sum of input overload currents on all port pins may

not exceed 50mA. The supply voltage must remain within the specified limits.

This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used

for CS output and the open drain function is not enabled.

The maximum current may be drawn while the respective signal line remains inactive.

The minimum current must be drawn in order to drive the respective signal line active.

The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is

illustrated in Figure 38 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs

disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: this implies I/O current is not considered. The device is

doing the following:

Fetching code from IRAM and XRAM1, accessing in read and write to both XRAM modules

Watchdog Timer is enabled and regularly serviced

RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles

Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling

Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)

ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5

All interrupts generated by XPWM, RTC, Timers and ADC are not serviced

10. The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is

illustrated in Figure 38 below. This parameter is tested at VDDmax and at maximum CPU clock frequency with all outputs

disconnected and all inputs at VIL or VIH, RSTIN pin at VIH1min: this implies I/O current is not considered. The device is

doing the following:

- Fetching code from all sectors of IFlash, accessing in read (few fetches) and write to XRAM

- Watchdog Timer is enabled and regularly serviced

- RTC is running with main oscillator clock as reference, generating a tick interrupts every 192 clock cycles

- Four channel of XPWM are running (waves period: 2, 2.5, 3 and 4 CPU clock cycles): no output toggling

- Five General Purpose Timers are running in timer mode with prescaler equal to 8 (T2, T3, T4, T5, T6)

- ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5

- All interrupts generated by XPWM, RTC, Timers and ADC are not serviced

11. The Idle mode supply current is a function of the operating frequency (fCPU is expressed in MHz). This dependency is

illustrated in Figure 37 below. These parameters are tested and at maximum CPU clock with all outputs disconnected and

all inputs at VIL or VIH, RSTIN pin at VIH1min.

12. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0V to 0.1V or at VDD

- 0.1V to VDD, VAREF = 0V, all outputs (including pins configured as outputs) disconnected. Also, the Main Voltage

Regulator is assumed to be off; if it is not, an additional 1mA must be added.

Table 56.

DC characteristics (continued)

Parameter

Symbol

Limit values

Unit

Test condition

Min

Max

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