68HC05PL4 datasheet(33/98 Pages) FREESCALE

33 / 98 page

April 30, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05PL4

RESETS

REV 2.0

5-1

SECTION 5

RESETS

This section describes the four reset sources and how they initialize the MCU. A

reset immediately stops the operation of the instruction being executed, initializes

certain control bits, and loads the program counter with a user de ned reset v ec-

tor address. The following conditions produce a reset:

•

Initial power-up of device (power-on reset)

•

A logic zero applied to the RESET pin (external reset)

•

Time-out of the COP watchdog (COP reset)

•

Fetch of an opcode from an address not in the memory map

(illegal address reset)

Figure 5-1. Reset Sources

5.1

POWER-ON RESET

A positive transition on the VDD pin generates a power on reset. The power-on

reset is strictly for conditions during powering up and cannot be used to detect

drops in power supply voltage.

RESET

LATCH

COP WATCHDOG

POWER-ON RESET

ILLEGAL ADDRESS RESET

INTERNAL

CLOCK

RST

TO CPU

AND

VDD

4-CYCLE

COUNTER

SUBSYSTEMS

ADDRESS BUS

Freescale Semiconductor, Inc.

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