68HC05PL4 datasheet(36/98 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

April 30, 1998

RESETS

MC68HC05PL4

5-4

REV 2.0

Use the following formula to calculate the COP time-out period:

COP Time-out Period = (prescaler x 256 x 8) ÷ fBUS

where prescaler is the Timer8 prescaler value

The clock input to the watchdog system is derived from the output of the Timer8,

therefore a reset or preset of Timer8 may affect the COP watchdog time-out

period.

The COP Watchdog reset will assert the pulldown device to pull the RESET pin

low for 3-4 cycles of the internal bus clock.

The COP reset can be enable or disable by the COPON bit in MISCR. The MISCR

is in Figure 5-5.

COPON — COP On

Since the COP Watchdog system is derived from the 8-bit Timer system, the

T8EN bit in the Timer8 Control and Status register (bit3 of $0D) must be set for

COPON bit to have any affect.

COPON can be set to enable the COP watchdog system. Once set, the watch-

dog system cannot be disabled other than by a power-on reset or external

reset. After a reset the COPON bit is cleared and the COP watchdog system is

disabled.

1 = COP Watchdog enabled.

0 = COP Watchdog disabled.

NOTE

The COP Watchdog system is not designed to operate in STOP mode, therefore it

should be disabled before entering STOP mode by clearing the COPON bit.

Entering STOP mode with COP watchdog enabled will cause an internal reset of

the MCU.

5.3.3 Illegal Address Reset

An opcode fetch from an address that is not in the ROM (locations $0E00–$1DFF

and $1FF0-$1FFF) or the RAM (locations $0020–$011F) generates an illegal

address reset. The illegal address reset will assert the pulldown device to pull the

RESET pin low for 3-4 cycles of the internal bus clock.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MICSR R

IRQEN

IRQS

TCMPEN TCAPEN

LED

COPON

POR

$001C W

RESET

00000000

Figure 5-5. Miscellaneous Control and Status Register (MICSR)

Freescale Semiconductor, Inc.

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