68HC05PL4 datasheet(49/98 Pages) FREESCALE

49 / 98 page

April 30, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05PL4

SYSTEM CLOCKS

REV 2.0

8-1

SECTION 8

SYSTEM CLOCKS

This section describes the system clock options for the MC68HC05PL4.

8.1

SYSTEM CLOCK SOURCE AND FREQUENCY OPTION

The operating bus frequency of the MCU is dependent on the clock source (OSC1

or internal RC) and the clock divider ratio. These are selected in the System Clock

Control Register (SYSCR).

SYSDIV1,SYSDIV2 — System Clock Divider Select

The SYSDIV1 and SYSDIV2 bits select the divide ratio for the clock source.

After power-on-reset, the default setting is divide by 2. Table 8-1 shows the

divide ratios.

CKSEL1,CKSEL2 — System Clock Source Select

The CKSEL1 and CKSEL2 bits select the system clock source for the MCU. After

power-on-reset, the default setting is internal RC. Table 8-2 shows the system

clock source options.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

SYSCR

SYSDIV1 SYSDIV2 CKSEL1

CKSEL2

FMODE

OSCF

RCF

CKOSC

$001D

POR

00101010

Figure 8-1. System Clock Control Register (SYSCR)

Table 8-1. System Clock Divider Select

SYSDIV1

SYSDIV2

DIV

Table 8-2. System Clock Source Select

CKSEL1

CKSEL2

Select Option

External from OSC1

Internal RC

External from OSC1 (with RC enabled)

Freescale Semiconductor, Inc.

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