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68HC05PL4 数据表(PDF) 12 Page - Freescale Semiconductor, Inc |
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68HC05PL4 数据表(HTML) 12 Page - Freescale Semiconductor, Inc |
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12 / 98 page  GENERAL RELEASE SPECIFICATION April 30, 1998 GENERAL DESCRIPTION MC68HC05PL4 1-2 REV 2.0 1.2 MCU BLOCK DIAGRAM Figure 1-1. MC68HC05PL4 Block Diagram NOTE A line over a signal name indicates an active low signal. Any reference to voltage, current, or frequency speci ed in the following sections will refer to the nominal values. The exact values and their tolerance or limits are speci ed in Electrical Speci cations section. USER ROM - 4k BYTES USER RAM - 256 BYTES ACCUMULATOR INDEX REGISTER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER M68HC05 CPU RESET 0 12 1 1 H I NZC OSC POWER OSC1 VDD VSS PB4- PB7 4 1 1 7 0 7 50 1 0 0 0 0 0 0 4 15 0 7 KEYBOARD INTERRUPT WATCHDOG SYSTEM PA6 PA5 PA4 PA3/TCMP PA2/TCAP PA1/DTMF PA0† 4 16-BIT PROGRAMMABLE TIMER VERY LOW FREQUENCY OSC (RC: 500kHz or 20kHz) (÷ N OPTIONAL) DTMF MODULE LED/IRQ LED DRIVE PC0 - PC7 8 8-BIT RELOADABLE EVENT TIMER PB0/KBI0 PB1/KBI1 PB2/KBI2 PB3/KBI3 OSC2†† ††Available on MC68HC05PL4B only. †Available on MC68HC05PL4 only. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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