SLAS366 datasheet(17/58 Pages) TI2

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3–5

initialization cycle that lasts for 132 MCLKs, during which the DSPs serial port is put in 3-state. For a cascaded system

the rise time of H/W RESET needs to be less than the MCLK period and should satisfy setup time requirement of 2 ns

with respect to MCLK rise-edge. In stand-alone-slave mode SCLK must be running during RESET. RESET must be

synchronized with MCLK in all cases.

3.5.2

Power Management

Most of the device (except the digital interface) enters the power-down mode when D7 and D6, in control register 3,

are set to 1. When the PWRDN pin is low, the entire device is powered down. In either case, register contents are

preserved and the output of the amplifier is held at midpoint voltage to minimize pops and clicks.

The amount of power drawn during software power down is higher than during a hardware power down because of

the current required to keep the digital interface active. Additional differences between software and hardware

power-down modes are detailed in the following paragraphs.

3.5.2.1 Software Power-Down

Data bits D7 and D6 of control register 3 are used by TLV320AIC14 to turn on or off the software power-down mode,

which takes effect in the next frame FS. The ADC and DAC can be powered down individually. In the software

power-down, the digital interface circuit is still active while the internal ADC and DAC channel and differential output

OUTP1 and OUTM1 are disabled, and DOUT is put in 3-state in the data frame only. Register data in the control frame

is still accepted via DIN, but data in the data frame is ignored. The device returns to normal operation when D7 and

D6 of control register 3 are reset.

3.5.2.2 Hardware Power-Down

The TLV320AIC14 requires the PWRDN signal to be synchronized with MCLK. When PWRDN is held low, the device

enters hardware power-down mode. In this state, the internal clock control circuit and the differential outputs are

disabled. All other digital I/Os are disabled and DIN can not accept any data input. The device can only be returned

to normal operation by holding PWRDN high. When not holding the device in the hardware power-down mode,

PWRDN must be tied high.

3.6

Digital Interface

3.6.1

Clock Source (MCLK, SCLK)

MCLK is the external master clock input. The clock circuit generates and distributes necessary clocks throughout the

device. SCLK is the bit clock used to receive and transmit data synchronously. When the device is in the master mode,

SCLK and FS are output and derived from MCLK in order to provide clocking the serial communications between the

device and a digital signal processor (DSP). When in the slave mode, SCLK and FS are inputs. In the non-turbo mode

(TURBO = 0), SCLK frequency is defined by:

SCLK = (16

× FS × #Devices × mode)

Where:

FS is the frame-sync frequency.

#Device is the number of the device in cascade.

Mode is equal to 1 for continuous data transfer mode and 2 for programming mode.

In turbo mode, see Section 3.8.3.

3.6.2

Serial Data Out (DOUT)

DOUT is placed in the high-impedance state after transmission of the LSB is completed. In data frame, the data word

is the ADC conversion result. In the control frame, the data is the register read results when requested by the

read/write (R/W) bit. If a register read is not requested, the low eight bits of the secondary word are all zeroes. Valid

data on DOUT is taken from the high-impedance state by the falling edge of frame-sync (FS). The first bit transmitted

on the falling edge of FS is the MSB of valid data.

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