SLAS366 datasheet(14/58 Pages) TI2

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3–2

3.2.4

Sigma-Delta DAC

The sigma-delta digital-to-analog converter is a sigma-delta modulator with 128/256/512 x oversampling. The DAC

provides high-resolution, low-noise performance using oversampling techniques. The oversampling ratio in DAC is

programmable to 256/512 using bits D4–D3 of control register 3, the default being 128. Oversampling ratio of 512

can be used when FS is a maximum of 8 Ksps and an oversampling ratio of 256 can be used when FS is a maximum

of 16 Ksps. M should be a multiple of 2 for an oversampling ratio of 256 and 4 for oversampling ratio of 512.

3.2.5

Interpolation Filter

The interpolation filters are either FIR filters or IIR filters selected by bit D5 of the control register 1. The FIR filter

provides linear-phase output with 16/f group delay, whereas the IIR filter generates nonlinear phase output with

negligible group delay. The interpolation filter resamples the digital data at a rate of 128/256/512 times the incoming

sample rate, based on the oversampling rate of DAC. The high-speed data output from the interpolation filter is then

used in the sigma-delta DAC. The BW of the filter is (0.45

× FS) and scales linearly with the sample rate.

3.2.6

Analog/Digital/Side-Tone Loopback

The analog and digital loopbacks provide a means of testing the data ADC/DAC channels and can be used for

in-circuit system level tests. The analog loopback always has the priority to route the DAC low pass filter output into

the analog input where it is then converted by the ADC to a digital word. The digital loopback routes the ADC output

to the DAC input on the device. Analog loopback is enabled by writing a 1 to bit D2 in the control register 1. Digital

loopback is enabled by writing a 1 to bit D1 in control register 1. The side-tone digital loopback attenuates the ADC

output and mixes it with the input of the DAC. The level of the side tone is set by DSTG, bits D5–D3 of the control

3.2.7

ADC PGA

TLV320AIC14 has a built-in PGA for controlling the signal levels at ADC outputs. ADC PGA gain setting can be

selected by writing into bits D5–D0 of register 5A. The PGA range of the ADC channel is 20 dB to –42 dB in steps

of 1 dB and mute. To avoid sudden jumps in signal levels with PGA changes, the gains are applied internally with

zero-crossovers.

3.2.8

DAC PGA

TLV320AIC14 has a built-in PGA for controlling the analog output signal levels in DAC channel. DAC PGA gain setting

can selected by writing into bits D5–D0 of register 5B. The PGA range of the DAC channel is 20 dB to –42 dB in steps

of 1 dB, and mute. To avoid sudden pop-sounds with power-up/down and gain changes the power-up/down and gain

changes for DAC channel are applied internally with zero-crossovers.

3.3

Analog Input/Output

The TLV320AIC14 has three programmable analog inputs and three programmable analog outputs. Bits D2–D1 of

control register 6 select the analog input source from MICIN, INP1/M1, or INP2/M2. All analog I/O is either

single-ended or differential. All analog input signals are self-biased to 1.35 V. The three analog outputs are configured

by bits D7, D6, D5, and D4–D3 of control register 6.

3.3.1

MIC Input

TLV320AIC14 supports single ended microphone input. This can be used by connecting the external single ended

source through ac coupling to the MICIN pin. This channel is selected by writing 01 or 10 into bits D2–D1 in control

Writing 01 into bits D2–D1 chooses self biased MICIN mode. In this mode the device internally self-biases the input

at 1.35V. For best noise performance the user should bias the microphone circuit using the BIAS voltage generated

by the device as shown in Figure 5–19.

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