SLAS366 datasheet(24/58 Pages) TI2

24 / 58 page

3–12

SCLK

DIN

DOUT

16–Bit DAC Data

16–Bit ADC Data

Slot Number 0

Slot Number 1

Figure 3–13. Standard Operation/Programming Mode: Stand-Alone Timing

SCLK

DIN/

DOUT

2n–1

2n–2

2n–3

Master Slave

n–2

Slave

n–3

Slave

Master Slave

n–2

Slave

n–3

Slave

Data Frame

Control Frame

(Register R/W)

16 SCLKs Per Slot

Slot

Number

NOTE: n is the total number of AIC14s in the cascade

Figure 3–14. Standard Operation/Programming Mode: Master-Slave Cascade Timing

3.8.2

Continuous Data Transfer Mode

The continuous data transfer mode, selected by setting bit D6 of the control register 1 to 1, contains conversion data

only. In continuous data transfer mode, the control frame is eliminated and the period of FS signal contains only the

data frame in which the 16-bit data is transferred contiguously, with no inactivity between bits. The control frame can

be reactivated by setting the LSB of DIN data to 1 if the data is in the 15+1 format. To return the programming mode

in the 16-bit DAC data format mode, write 0 in bit D6 of control register 1 using I2C or S2C, or do a hardware reset

to come out of continuous data transfer mode. The continuous data transfer mode can support the TI DSP McBSPs

autobuffering unit (ABU) operation in which the serial port interrupts are not generated with each word transferred

to prevent CPU’s ISR overheads.

SLAS366 数据表(PDF) 24 Page - Texas Instruments

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SLAS366 数据表(PDF) 24 Page - Texas Instruments

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