SLAS366 datasheet(12/58 Pages) TI2

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2–2

2.2

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

IOVDD

Digital I/O power supply

IOVSS

Digital I/O ground

MCLK

Master clock. MCLK derives the internal clocks of the sigma-delta analog interface circuit.

MICIN

MIC preamplifier input. It must be connected to AVSS if not used.

M/S

Master/slave select input. When M/S is high, the device is the master, and when low it is a slave.

OUTM1

Inverting output of the DAC. OUTM1 is functionally identical with and complementary to OUTP1. This differential

output can drive a minimum load of 600

Ω. This output can also be used alone for single-ended operation.

13, 14,

OUTP1

Noninverting output of the DAC. This differential output can drive a minimum load of 600

Ω. This output can also be

used alone for single-ended operation.

PWRDN

Power down. When PWRDN is pulled low, the device goes into a power-down mode, the serial interface is disabled,

and most of the high-speed clocks are disabled. However, all the register values are sustained and the device

resumes full-power operation without reinitialization when PWRDN is pulled high again. PWRDN resets the

counters only and preserves the programmed register contents.

RESET

Hardware reset. The reset function is provided to initialize all of the internal registers to their default values. The

serial port is configured to the default state accordingly.

SCL

Programmable host port (I2C or S2C) clock input.

SCLK

I/O

Shift clock. SCLK signal clocks serial data into DIN and out of DOUT during the frame-sync interval. When

configured as an output (M/S high), SCLK is generated internally by multiplying the frame-sync signal frequency by

16 and the number of codecs in cascade in standard and continuous mode. When configured as an input (M/S low),

SCLK is generated externally and must be synchronous with the master clock and frame sync.

SDA

I/O

Programmable host port (I2C or S2C) data line.

2.3

Definitions and Terminology

Data Transfer

Interval

The time during which data is transferred from DOUT and to DIN. The interval is 16 shift clocks and the data

transfer is initiated by the falling edge of the FS signal in standard and continuous mode.

Signal Data

This refers to the input signal and all of the converted representations through the ADC channel and the

signal through the DAC channel to the analog output. This is contrasted with the purely digital software

control data.

Frame Sync

Frame sync refers only to the falling edge of the signal FS that initiates the data transfer interval

Frame Sync and

Sampling Period

Frame sync and sampling period is the time between falling edges of successive FS signals.

The sampling frequency

ADC Channel

ADC channel refers to all signal processing circuits between the analog input and the digital

conversion result at DOUT.

DAC channel

DAC channel refers to all signal processing circuits between the digital data word applied to DIN and the

differential output analog signal available at OUTP1 and OUTM1.

Dxx

Bit position in the primary data word (xx is the bit number)

DSxx

Bit position in the secondary data word (xx is the bit number)

PGA

Programmable gain amplifier

IIR

Infinite impulse response

FIR

Finite impulse response

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