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AMC7832IPAPR 数据表(PDF) 13 Page - Texas Instruments |
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AMC7832IPAPR 数据表(HTML) 13 Page - Texas Instruments |
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13 / 74 page ![]() AMC7832 www.ti.com SLAS836 – MARCH 2014 7.6 Timing Requirements - Serial Interface (1) (2) AVDD = DVDD = +4.5 to +5.5-V, AVCC = +12-V, AVEE = -12-V, AGND = DGND = AVSSA,B,C,D = 0-V, DAC output range = 0 to +10-V for all groups, no load on the DACs, TA = -40°C to +105°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOVDD = +1.8-V to +2.7-V fSCLK SCLK frequency 15 MHz tP SCLK period 66.67 ns tPH SCLK pulse width high 27 ns tPL SCLK pulse width low 27 ns tSU SDI setup 10 ns tH SDI hold 10 ns tODZ SDO driven to tri-state 0 15 ns tOZD SDO tri-state to driven 0 20 ns tOD SDO output delay 0 20 ns tCSS CS setup 5 ns tCSH CS hold 20 ns tIAG Inter-access gap 10 ns IOVDD = +2.7-V to +5.5-V fSCLK SCLK frequency 20 MHz tP SCLK period 50 ns tPH SCLK pulse width high 22.5 ns tPL SCLK pulse width low 20 ns tSU SDI setup 10 ns tH SDI hold 10 ns tODZ SDO driven to tri-state 0 9 ns tOZD SDO tri-state to driven 0 12 ns tOD SDO output delay 0 15 ns tCSS CS setup 5 ns tCSH CS hold 20 ns tIAG Inter-access gap 10 ns (1) Specified by design and characterization. Not tested during production. (2) SDO loaded with 10-pF load capacitance for SDO timing specifications. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: AMC7832 |
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