 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AMC7836IPAPRG4 数据表(PDF) 33 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AMC7836IPAPRG4 数据表(HTML) 33 Page - Texas Instruments |
|
|
33 / 91 page  ADCTRIG DAV First CONVERSION of the channels specified in the ADC MUX Registers Second CONVERSION of the channels specified in the ADC MUX Registers Third CONVERSION of the channels specified in the ADC MUX Registers 1 st trigger 2 nd trigger 3 rd trigger CS Read Command Read Command > 2 µs First CONVERSION of the channels specified in the ADC MUX Registers Second CONVERSION of the channels specified in the ADC MUX Registers 1 st internal trigger 2 nd internal trigger Read Command Trigger Command Read Command Trigger Command > 2 µs DAV CS 33 AMC7836 www.ti.com SLAS986D – NOVEMBER 2014 – REVISED FEBRUARY 2018 Product Folder Links: AMC7836 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated 7.3.2.3 ADC Synchronization A trigger signal must occur for the ADC to enter and exit the IDLE state. The ADC trigger can be generated either through software (ICONV bit in the ADC trigger register, 0xC0) or hardware (GPIO2/ADCTRIG, pin 9). To use the GPIO2/ADCTRIG pin as an ADC trigger, the pin must be configured accordingly in the GPIO configuration register (address 0x12). When the pin is configured as a trigger, a falling edge on it begins the sampling and conversion of the ADC. In auto mode the ADC and temperature data registers (0x20 through 0x4B) are accessed by first issuing an ADC UPDATE command in the register update register (address 0x0F). The ADC UPDATE command ensures the latest available data for each input channel can be accessed without the need for complex synchronization schemes between the AMC7836 device and the host controller. A single ADC UPDATE command updates all ADC and temperature data registers. Therefore issuing multiple UPDATE commands is not necessary when reading more than one ADC data register. NOTE The ADC UPDATE command and accessing of the ADC and Temperature data registers does not interfere with the conversion process which ensures continuous ADC operation. In direct mode the ADC and temperature data registers (0x20 through 0x4B) should only be accessed while the ADC is in the IDLE state (see Figure 53). Although the total update time can be easily calculated, the device provides a data-available indicator signal to track the ADC status. Failure to satisfy the synchronization requirements could lead to erroneous data reads. The data-available indicator signal is output through the GPIO3/DAV pin and as a data-available flag that is accessible through the serial interface (DAVF bit in the general status register, 0x72). The GPIO3/DAV pin must be configured in the GPIO configuration register (address 0x12) as an interrupt. After a direct-mode conversion is complete and the ADC returns to the IDLE state, the DAVF bit is immediately set to 1 and the DAV pin is active (low) which indicates that new data is available. The pin and flag are cleared automatically when a new conversion begins or one of the ADC data or temperature data registers is accessed. a) Direct Mode, Software Trigger b) Direct Mode, Hardware Trigger Figure 53. ADC Direct-Mode Trigger Synchronization |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
