AMC7836IPAPRG4 datasheet(64/91 Pages) TI2

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AMC7836

SLAS986D – NOVEMBER 2014 – REVISED FEBRUARY 2018

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7.6.9.3 General Status Register (address = 0x72) [reset = 0x0C]

Figure 97. General Status Register (R)

AVSSD

AVSSC

AVSSB

AVSSA

ADC_IDLE

Reserved

GALR

DAVF

—

R-1

R-0

Table 45. General Status Register Field Descriptions

Bit

Field

Type

Reset

Description

AVSSD

—

This bit is the auto-range detection output for DAC group D. This

bit is set to 1 when AVSSD < AVSSTH (–10- to 0-V output range),

and 0 when AVSSD > AVSSTH (0- to 5-V output range).

AVSSC

—

This bit is the auto-range detection output for DAC group C. This

bit is set to 1 when AVSSC < AVSSTH (–10- to 0-V output range),

and 0 when AVSSC > AVSSTH (0- to 5-V output range).

AVSSB

—

This bit is the auto-range detection output for DAC group B. This

bit is set to 1 when AVSSB < AVSSTH (–10- to 0-V output range),

and 0 when AVSSB > AVSSTH (0- to 5-V output range).

AVSSA

—

This bit is the auto-range detection output for DAC group A. This

bit is set to 1 when AVEE < AVSSTH (–10- to 0-V output range),

and 0 when AVEE > AVSSTH (0- to 5-V output range).

ADC_IDLE

ADC Idle indicator.

Auto mode: 1 by default; goes to 0 once the ADC is

triggered and is running. Remains 0 until ADC is stopped,

then ADC_IDLE returns to 1.

Direct mode: 1 by default; goes to 0 once the ADC is

triggered and direct conversions are running and returns to

1 when direct mode conversions are completed.

Reserved

Reserved for factory use

GALR

Global alarm bit.

This bit is the OR function or all individual alarm bits of the

status register. This bit is set to 1 when any alarm condition

occurs and remains set until the status register is read. This bit

is cleared after reading the Status Register.

DAVF

ADC Data available flag bit. Direct mode only. Always cleared in

Auto mode.

0: ADC conversion is in progress or ADC is in Auto mode

1: ADC conversions are complete and new data is available

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