AMC7836IPAPRG4 datasheet(78/91 Pages) TI2

78 / 91 page

-15

-10

-5

Time (µs)

10nF, Rising Edge

200pF, Rising Edge

C001

-15

-10

-5

Time (µs)

10nF, Falling Edge

200pF, Falling Edge

C001

AMC7836

SLAS986D – NOVEMBER 2014 – REVISED FEBRUARY 2018

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During the conversion, the input current per channel varies with the total update time which is determined by the

number and type of channels (NCH) and the conversion rate setting of the CONV-RATE bit in the ADC

configuration register (address 0x10).

NOTE

The source of the analog input voltage must be able to charge the input capacitance to a

12-bit settling level within the acquisition time.

8.2.2.2 DAC Output Range Selection

The AMC7836 device includes 16 DACs split into four groups, each with four DACs. All of the DACs in a given

group share the same output voltage range. The output range for each DAC group is independent and is

programmable to either –10 to 0 V, –5 to 0 V, 0 to 10 V or 0 to 5 V. The DAC output ranges are configured by

following the configuration settings listed in Table 1.

Each DAC includes an output buffer is capable of generating rail-to rail voltages. The Electrical Characteristics:

DAC table lists the maximum source and sink capability of this internal amplifier. The graphs in the Application

Curves section show the relationship of both stability and settling time with different capacitive loading structures.

8.2.3 Application Curves

Code 0x400 to 0xC00 to within ½ LSB

Figure 119. DAC Settling Time vs Load Capacitance

Code 0xC00 to 0x400 to within ½ LSB

Figure 120. DAC Settling Time vs Load Capacitance

9 Power Supply Recommendations

The preferred (not required) pin order for applying power is IOVDD, DVDD and AVDD, AVCC and lastly AVEE,

AVSSB, AVSSC, and AVSSD.When power sequencing, ensure that all digital pins are not powered or in an active

state while the IOVDD pin ramps. Proper sequencing of the digital pins can be accomplished by attaching 10-kΩ

pullup resistors to the IOVDD pin, or pulldown resistors to the DGND pin. See the supply voltage ranges in the

Recommended Operating Conditions table.

In applications where a negative voltage is applied to AVEE, AVSSB, AVSSC, and AVSSD first, the user may notice

some small negative voltages at other supply pins, such as the AVDD, DVDD, and AVCC pins. The negative

voltages at the supply pins may exceed the values listed in the Absolute Maximum Ratings table, but because

these voltages are created from intrinsic circuitry, the voltage levels are safe for operation.

In the case where all DAC outputs are in clamp state with AVEE = AVSSB = AVSSC = AVSSD = –12 V, the

negative voltage observed on the other supply pins can be as low as –620 mV.

Although these negative voltages are observed on the pins, the user must still adhere to the guidelines specified

in the Absolute Maximum Ratings table and verify that the inputs are driven within the range specified in the

table. The user should also ensure that current is only applied when operating with voltages between the ranges

listed in the Absolute Maximum Ratings table.

AMC7836IPAPRG4 数据表(PDF) 78 Page - Texas Instruments

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