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AMC7836IPAPRG4 数据表(PDF) 65 Page - Texas Instruments |
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AMC7836IPAPRG4 数据表(HTML) 65 Page - Texas Instruments |
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65 / 91 page ![]() 65 AMC7836 www.ti.com SLAS986D – NOVEMBER 2014 – REVISED FEBRUARY 2018 Product Folder Links: AMC7836 Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated 7.6.10 GPIO: Address 0x7A 7.6.10.1 GPIO Register (address = 0x7A) [reset = 0xFF] Figure 98. GPIO Register (R/W) 7 6 5 4 3 2 1 0 GPIO-7 GPIO-6 GPIO-5 GPIO-4 GPIO-3 GPIO-2 GPIO-1 GPIO-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 Table 46. GPIO Register Field Descriptions Bit Field Type Reset Description 7 GPIO-7 R/W 1 For write operation the GPIO pin operates as an output. Writing a 1 to the GPIO-n bit sets the GPIO-N pin to high impedance. Writing a 0 sets the GPIO-n pin to logic low. For read operations the GPIO pin operates as an input. Read the GPIO-n bit to receive the status of the GPIO-n pin. The GPIO-n pin has 48-k Ω input impedance to IOVDD. 6 GPIO-6 R/W 1 5 GPIO-5 R/W 1 4 GPIO-4 R/W 1 3 GPIO-3 R/W 1 2 GPIO-2 R/W 1 1 GPIO-1 R/W 1 0 GPIO-0 R/W 1 7.6.11 Out-Of-Range ADC Thresholds: Address 0x80 through 0x93 The unipolar analog inputs (LV_ADC16 to LV_ADC20) and the local temperature sensor implement an out-of- range alarm function. The Upper-Thresh and Lower-Thresh registers define the upper bound and lower bounds for these inputs. This window determines whether the analog input or temperature is out-of-range. When the input is outside the window, the corresponding CH-ALR-n bit in the Status Register is set to 1. For normal operation, the value of the upper threshold must be greater than the value of lower threshold; otherwise, an alarm is always indicated. The analog input threshold values are specified in straight binary format while the local temperature ones are specified in two’s complement format. 7.6.11.1 ADCn-Upper-Thresh (Low Byte) Register (address = 0x80 through 0x93) [reset = 0xFF] Figure 99. ADCn-Upper-Thresh (Low Byte) Register (R/W) 7 6 5 4 3 2 1 0 THRUn(7:0) R/W-All ones Table 47. ADCn-Upper-Thresh (Low Byte) Register Field Descriptions Bit Field Type Reset Description 7-0 THRUn(7:0) R/W All ones Sets 12-bit upper threshold value for the ADC_n channel in straight binary format. |
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