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AMC7836IPAPRG4 数据表(PDF) 13 Page - Texas Instruments

部件名 AMC7836IPAPRG4
功能描述  AMC7836 High-Density, 12-Bit Analog Monitor and Control Solution With Multichannel ADC, Bipolar DACs, Temperature Sensor, and GPIO Ports
PDF  91 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

AMC7836IPAPRG4 数据表(HTML) 13 Page - Texas Instruments

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AMC7836
www.ti.com
SLAS986D – NOVEMBER 2014 – REVISED FEBRUARY 2018
Product Folder Links: AMC7836
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
(1)
Specified by design and characterization. Not tested during production.
(2)
See Figure 1 and Figure 2.
(3)
SDO loaded with 10 pF load capacitance for SDO timing specifications.
(4)
See Figure 2.
(5)
Specified by design; not subject to production testing. See the ADC Sequencing section for more details.
6.8 Timing Requirements
AVDD = DVDD = 4.7 to 5.5 V, AVCC = 12 V, AVEE = –12 V, AGND = DGND = AVSSB = AVSSC = AVSSD = 0 V, DAC output range
= 0 to 10 V for all groups, no load on the DACs, TA = –40°C to 105°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
SERIAL INTERFACE(1)
ƒ(SCLK)
SCLK frequency
IOVDD = 1.8 to 2.7 V
15
MHz
IOVDD = 2.7 to 5.5 V
20
tp
SCLK period(2)
IOVDD = 1.8 to 2.7 V
66.67
ns
IOVDD = 2.7 to 5.5 V
50
tPH
SCLK pulse width high(2)
IOVDD = 1.8 to 2.7 V
30
ns
IOVDD = 2.7 to 5.5 V
23
tPL
SCLK pulse width low(2)
IOVDD = 1.8 to 2.7 V
30
ns
IOVDD = 2.7 to 5.5 V
23
tsu
SDI setup(2)
IOVDD = 1.8 to 2.7 V
10
ns
IOVDD = 2.7 to 5.5 V
10
th
SDI hold(2)
IOVDD = 1.8 to 2.7 V
10
ns
IOVDD = 2.7 to 5.5 V
10
t(ODZ)
SDO driven to tri-
state(3)(4)
IOVDD = 1.8 to 2.7 V
0
15
ns
IOVDD = 2.7 to 5.5 V
0
9
t(OZD)
SDO tri-state to
driven(3)(4)
IOVDD = 1.8 to 2.7 V
0
23
ns
IOVDD = 2.7 to 5.5 V
0
15
t(OD)
SDO output delay(3)(4)
IOVDD = 1.8 to 2.7 V
0
23
ns
IOVDD = 2.7 to 5.5 V
0
15
tsu(CS)
CS setup(2)
IOVDD = 1.8 to 2.7 V
5
ns
IOVDD = 2.7 to 5.5 V
5
th(CS)
CS hold(2)
IOVDD = 1.8 to 2.7 V
20
ns
IOVDD = 2.7 to 5.5 V
20
t(IAG)
Inter-access gap(2)
IOVDD = 1.8 to 2.7 V
10
ns
IOVDD = 2.7 to 5.5 V
10
DIGITAL LOGIC
Reset delay; delay-to-normal operation from reset
100
250
µs
Power-down recovery time
70
µs
Clamp shutdown delay
100
µs
Convert pulse width
20
ns
Reset pulse width
20
ns
ADC WAIT state(5); the wait time from when the ADC enters the IDLE state
to when the ADC is ready for trigger
2
µs



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