XIO2001IPNP datasheet(39/145 Pages) TI2

39 / 145 page

Table 8-8. EEPROM Register Loading Map (continued)

SERIAL EEPROM WORD

ADDRESS

BYTE DESCRIPTION

16h

PCI C7h, control and diagnostic register, byte 3

17h

PCI C8h, control and diagnostic register, byte 0

18h

PCI C9h, control and diagnostic register, byte 1

19h

PCI CAh, control and diagnostic register, byte 2

1Ah

PCI CBh, control and diagnostic register, byte 3

1Bh

Reserved—no bits loaded

1Ch

Reserved—no bits loaded

1Dh

PCI E0h, serial IRQ mode control

1Eh

PCI E2h, serial IRQ edge control, byte 0

1Fh

PCI E3h, serial IRQ edge control, byte 1

20h

PCI E8h, PFA_REQ_LENGTH_LIMIT

21h

PCI E9h, PFA_REQ_CNT_LIMIT

22h

PCI EAh, CACHE_TMR_XFR_LIMIT

23h

PCI ECh, CACHE_TIMER_LOWER_LIMIT, Byte 0

24h

PCI EDh, CACHE_TIMER_LOWER_LIMIT, Byte 1

25h

PCI EEh, CACHE_TIMER_UPPER_LIMIT, Byte 0

26h

PCI EFh, CACHE_TIMER_UPPER_LIMIT, Byte 1

27h

End-of-list indicator (80h)

This format must be explicitly followed for the bridge to correctly load initialization values from a serial EEPROM.

All byte locations must be considered when programming the EEPROM.

The serial EEPROM is addressed by the bridge at slave address 1010 000b. This slave address is internally

hardwired and cannot be changed by the system designer. Therefore, all three hardware address bits for the

EEPROM are tied to VSS to achieve this address. The serial EEPROM in the sample application circuit (Figure

8-9) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to the chip, and

the sample application shows these terminal inputs tied to VSS.

During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is

asserted. After the download is finished, bit 0 (ROM_ERR) in the serial-bus control and status register may be

monitored to verify a successful download.

8.3.8.4 Accessing Serial-Bus Devices Through Software

The bridge provides a programming mechanism to control serial-bus devices through system software. The

programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 8-9 lists the

registers that program a serial-bus device through software.

Table 8-9. Registers Used To Program Serial-Bus Devices

PCI OFFSET

DESCRIPTION

B0h

Serial-bus data (see

Section 8.4.56)

Contains the data byte to send on write commands or the received data byte on read

commands.

B1h

Serial-bus word address

(see Section 8.4.57)

The content of this register is sent as the word address on byte writes or reads. This register is

not used in the quick command protocol. Bit 7 (PROT_SEL) in the serial-bus control and status

B2h

Serial-bus slave address

(see Section 8.4.58)

Write transactions to this register initiate a serial-bus transaction. The slave device address

and the R/ W command selector are programmed through this register.

B3h

Serial-bus control and

status (see Section 8.4.59)

Serial interface enable, busy, and error status are communicated through this register. In

addition, the protocol-select bit (PROT_SEL) and serial-bus test bit (SBTEST) are programmed

through this register.

www.ti.com

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

Submit Document Feedback

Product Folder Links: XIO2001

XIO2001IPNP 数据表(PDF) 39 Page - Texas Instruments

XIO2001IPNP 数据表(HTML) 39 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载