XIO2001IPNP datasheet(4/145 Pages) TI2

4 / 145 page

REVISION

DATE

REVISION

NUMBER

REVISION COMMENTS

9/2014

Changed pin F10 From: VDD_15 To: VDD_15_PLL in the ZGU package

Changed pin F11 From: VDD_15 To: VDD_15_PLL in the ZAJ package

Changed pin 84 From: VDDA_15 To: VDD_15_PLL in the PNP package

Changed the pin name from VDD_15_PULL to VDD_15_PLL in the Pin Functions table.

Changed PCIR description in the Pin Functions table From: "Connect this terminals to the secondary PCI

bus..." To: "Connect each one of these terminals to the secondary PCI bus.."

Deleted text from the LOCK pin description in the Pin Functions table: "when bit 12 (LOCK_EN) is set in

the general control register (see Section 8.4.66)."

Changes from Revision I (September 2014) to Revision J (January 2021)

Page

• NOTE: The device in the MicroStar Jr. BGA packaging were redesigned using a laminate nFBGA package.

This nFBGA package offers datasheet-equivalent electrical performance. It is also footprint equivalent to the

MicroStar Jr. BGA. The new package designator in place of the discontinued package designator will be

updated throughout the datasheet......................................................................................................................1

• Changed u*jr ZGU to nFBGA ZWS.................................................................................................................... 1

• Changed u*jr ZGU to nFBGA ZWS.................................................................................................................... 8

• Changed PCIE RX max abs in the Section 6.1 table From: 0.6 to 1.2............................................................. 15

• Changed u*jr ZGU to nFBGA ZWS Thermal Model and Corrected ZGU to ZAJ part numbers....................... 16

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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