XIO2001IPNP datasheet(49/145 Pages) TI2

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Table 8-15. Device Control Base Address Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:12

ADDRESS

R or RW

Memory Address. The memory address field for XIO2001 uses 20 read/write bits indicating

that 4096 bytes of memory space are required. While less than this is actually used, typical

systems will allocate this space on a 4K boundary. If the BAR0_EN bit (bit 5 at C8h) is ‘0’,

then these bits are read-only and return zeros when read. If the BAR0_EN bit is ‘1’, then

these bits are read/write.

11:4

RSVD

Reserved. These bits are read-only and return 00h when read.

PRE_FETCH

Prefetchable. This bit is read-only 0b indicating that this memory window is not prefetchable.

2:1

MEM_TYPE

Memory type. This field is read-only 00b indicating that this window can be located anywhere

in the 32-bit address space.

MEM_IND

Memory space indicator. This field returns 0b indicating that memory space is used.

8.4.12 Primary Bus Number Register

This read/write register specifies the bus number of the PCI bus segment that the PCI Express interface is

connected to.

PCI register offset:

18h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

8.4.13 Secondary Bus Number Register

This read/write register specifies the bus number of the PCI bus segment that the PCI interface is connected to.

The bridge uses this register to determine how to respond to a type 1 configuration transaction.

PCI register offset:

19h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

8.4.14 Subordinate Bus Number Register

This read/write register specifies the bus number of the highest number PCI bus segment that is downstream of

the bridge. The bridge uses this register to determine how to respond to a type 1 configuration transaction.

PCI register offset:

1Ah

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

www.ti.com

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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