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XIO2001IPNP 数据表(PDF) 89 Page - Texas Instruments |
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XIO2001IPNP 数据表(HTML) 89 Page - Texas Instruments |
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89 / 145 page  Table 8-59. Pre-Fetch Agent Request Limits Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:12 RSVD R Reserved. Returns 0h when read. 11:8(1) PFA_REQ_ CNT_LIMIT RW Request count limit. Determines the number of Pre-Fetch reads that takes place in each burst. 4'h0 = Auto-prefetch agent is disabled. 4'h1 = Thread is limited to one buffer. No auto-prefetch reads will be generated. 4'h2:F = Thread will be limited to initial read and (PFA_REQ_CNT_LIMIT – 1) 7:6 PFA_CPL_CACHE_ MODE RW Completion cache mode. Determines the rules for completing the caching process. 00 = No caching. • Pre-fetching is disabled. • All remaining read completion data will be discarded after any of the data has been returned to the PCI master. 01 = Light caching. • Pre-fetching is enabled. • All remaining read completion data will be discarded after data has been returned to the PCI master and the PCI master terminated the transfer. • All remaining read completion data will be cached after data has been returned to the PCI master and the bridge has terminated the transfer with RETRY. 10 = Full caching. • Pre-fetching is enabled. • All remaining read completion data will be cached after data has been returned to the PCI master and the PCI master terminated the transfer. • All remaining read completion data will be cached after data has been returned to the PCI master and the bridge has terminated the transfer with RETRY. 11 = Reserved. 5:4 RSVD R Reserved. Returns 00b when read. 3:0 PFA_REQ_LENGT H_LIMIT RW Request Length Limit. Determines the number of bytes in the thread that the pre-fetch agent will read for that thread. 0000 = 64 bytes 0001 = 128 bytes 0010 = 256 bytes 0011 = 512 bytes 0100 = 1 Kbytes 0101 = 2 Kbytes 0110 = 4 Kbytes 0111 = 8 Kbytes 1000:1111 = Reserved (1) These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset. 8.4.77 Cache Timer Transfer Limit Register This register is used to set the number of PCI cycle starts that have to occur without a read hit on the completion data buffer, before the cache data can be discarded. See Table 8-60 for a complete description of the register contents. PCI register offset: EAh Register type: Read/Clear Default value: 0008h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Table 8-60. Cache Timer Transfer Limit Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:8 RSVD R Reserved. Returns 00h when read. www.ti.com XIO2001 SCPS212J – MAY 2009 – REVISED JANUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 89 Product Folder Links: XIO2001 |
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