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XIO2001IPNP 数据表(PDF) 13 Page - Texas Instruments |
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XIO2001IPNP 数据表(HTML) 13 Page - Texas Instruments |
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13 / 145 page  Miscellaneous Pins SIGNAL ZWS BALL NO. ZAJ BALL NO. PNP PIN NO. I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS DESCRIPTION CLKRUN_ EN A13 C11 96 I LV CMOS VDD_33 Optional pullup/ pulldown resistor Clock run enable 0 = Clock run support disabled 1 = Clock run support enabled EXT_ARB_EN C10 A12 97 I LV CMOS VDD_33 Optional pullup/ pulldown resistor External arbiter enable 0 = Internal arbiter enabled 1 = External arbiter enabled GPIO0 // CLKRUN N09 N09 55 I/O LV CMOS VDD_33 Optional pullup resistor General-purpose I/O 0/clock run. This terminal functions as a GPIO controlled by bit 0 (GPIO0_DIR) in the GPIO control register (see Section 8.4.60) or the clock run terminal. This terminal is used as clock run input when the bridge is placed in clock run mode. Note: In clock run mode, an external pullup resistor is required to prevent the CLKRUN signal from floating. Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input. GPIO1 // PWR_ OVRD M09 M09 56 I/O LV CMOS VDD_33 – General-purpose I/O 1/power override. This terminal functions as a GPIO controlled by bit 1 (GPIO1_DIR) in the GPIO control register (see Section 8.4.60) or the power override output terminal. GPIO1 becomes PWR_OVRD when bits 22:20 (POWER_OVRD) in the general control register are set to 001b or 011b (see Section 8.4.66). Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input. GPIO2 N10 N10 57 I/O LV CMOS VDD_33 – General-purpose I/O 2. This terminal functions as a GPIO controlled by bit 2 (GPIO2_DIR) in the GPIO control register (see Section 8.4.60). Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input. GPIO3 // SDA N11 L08 58 I/O LV CMOS VDD_33 Optional pullup resistor GPIO3 or serial-bus data. This terminal functions as serial-bus data if a pullup resistor is detected on SCL or when the SBDETECT bit is set in the Serial Bus Control and Status Register (see Section 8.4.59). If no pullup is detected then this terminal functions as GPIO3. Note: In serial-bus mode, an external pullup resistor is required to prevent the SDA signal from floating. www.ti.com XIO2001 SCPS212J – MAY 2009 – REVISED JANUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: XIO2001 |
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