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XIO2001IPNP 数据表(PDF) 48 Page - Texas Instruments

部件名 XIO2001IPNP
功能描述  XIO2001 PCI Express to PCI Bus Translation Bridge
PDF  145 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

XIO2001IPNP 数据表(HTML) 48 Page - Texas Instruments

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8.4.8 Primary Latency Timer Register
This read-only register has no meaningful context for a PCI Express device and returns 00h when read.
PCI register offset:
0Dh
Register type:
Read only
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
8.4.9 Header Type Register
This read-only register indicates that this function has a type one PCI header. Bit 7 of this register is 0b indicating
that the bridge is a single-function device.
PCI register offset:
0Eh
Register type:
Read only
Default value:
01h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
1
8.4.10 BIST Register
Since the bridge does not support a built-in self test (BIST), this read-only register returns the value of 00h when
read.
PCI register offset:
0Fh
Register type:
Read only
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
8.4.11 Device Control Base Address Register
This register programs the memory base address that accesses the device control registers. By default, this
register is read only. If bit 5 of the Control and Diagnostic Register 2 (see Section 8.4.64) is set, then the bits
31:12 of this register become read/write. See Table 8-15 for a complete description of the register contents.
PCI register offset:
10h
Register type:
Read-only, Read/Write
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XIO2001
SCPS212J – MAY 2009 – REVISED JANUARY 2021
www.ti.com
48
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: XIO2001



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