XIO2001IPNP datasheet(41/145 Pages) TI2

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After the deassertion of PERST, the XIO2001 compares the information within the CSPLS and CSPLV fields of

the device capabilities register to the minimum power scale (MIN_POWER_SCALE) and minimum power value

(MIN_POWER_VALUE) fields in the general control register at offset D4h. See Section 8.4.66, General Control

MIN_POWER_VALUE fields, respectively, then the bridge takes the appropriate action that is defined below.

The power usage action is programmable within the bridge. The general control register includes a 3-bit

POWER_OVRD field. This field is programmable to the following options:

1. Ignore slot power limit fields.

2. Assert the PWR_OVRD terminal.

3. Disable secondary clocks as specified by the clock mask register at offset D9h (see Section 8.4.68).

4. Disable secondary clocks as specified by the clock mask register and assert the PWR_OVRD terminal.

5. Respond with unsupported request to all transactions except type 0/1 configuration transactions and set slot

power limit messages

8.3.13 PCI Express and PCI Bus Power Management

The bridge supports both software-directed power management and active state power management through

standard PCI configuration space. Software-directed registers are located in the power management capabilities

structure located at offset 48h (see Section 8.4.32). Active state power management control registers are located

in the PCI Express capabilities structure located at offset 70h (see Section 8.4.42).

During software-directed power management state changes, the bridge initiates link state transitions to L1 or

L2/L3 after a configuration write transaction places the device in a low power state. The power management

state machine is also responsible for gating internal clocks based on the power state. Table 8-10 identifies the

relationship between the D-states and bridge clock operation.

Table 8-10. Clocking In Low Power States

CLOCK SOURCE

D0/L0

D1/L1

D2/L1

D3/L2/L3

PCI express reference clock input (REFCLK)

On/Off

Internal PCI bus clock to bridge function

Off

The link power management (LPM) state machine manages active state power by monitoring the PCI Express

transaction activity. If no transactions are pending and the transmitter has been idle for at least the minimum time

required by the PCI Express Specification, then the LPM state machine transitions the link to either the L0s or L1

state. By reading the bridge’s L0s and L1 exit latency in the link capabilities register, the system software may

make an informed decision relating to system performance versus power savings. The ASLPMC field in the link

control register provides an L0s only option, L1 only option, or both L0s and L1 option.

8.3.14 Auto Pre-Fetch Agent

The auto pre-fetch agent is an internal logic module that will generate speculative read requests on behalf of a

PCI master to improve upstream memory read performance.

The auto pre-fetch agent will generate a read thread on the PCI-express bus when it receives an upstream

prefetchable memory read request on the PCI bus. A read thread is a sequence of one or more read requests

with contiguous read addresses. The first read of thread will be started by a master on the PCI bus requesting a

read that is forwarded to the root complex by the bridge. Each subsequent read in the thread will be initiated by

the auto pre-fetch agent. Each subsequent read will use the address that immediately follows the last address of

data in the previous read of the thread. Each read request in the thread will be assigned to an upstream request

processor. The pre-fetch agent can issue reads for two threads at one time, alternating between the threads.

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XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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