XIO2001IPNP datasheet(76/145 Pages) TI2

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BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 8-47. Control and Diagnostic Register 2 Description

BIT

FIELD NAME ACCESS

DESCRIPTION

31:24(1) N_FTS_

ASYNC_CLK

N_FTS for asynchronous clock. When bit 6 (CCC) of the link control register (offset A0h, see Section

8.4.54) is clear, the value in this field is the number of FTS that are sent on a transition from L0s to L0.

This field shall default to 32h.

23:16(1) N_FTS_

COMMON_

CLK

N_FTS for common clock. When bit 6 (CCC) of the link control register (offset A0h, see Section

8.4.54) is set, the value in this field is the number of FTS that are sent on a transition from L0s to L0.

This field defaults to 14h.

15:13

PHY_REV

PHY revision number

12:8(1) LINK_NUM

Link number

7(1)

EN_L2_PWR_

SAVE

Enable L2 Power Savings

Power savings not enabled when in L2

Power savings enabled when in L2.

RSVD

Reserved. Returns 0b when read.

5(1)

BAR0_EN

BAR 0 Enable.

0 =

1 =

BAR at offset 10h is disabled (default)

BAR at offset 10h is enabled

4:0(1)

RSVD

Reserved. Bits 4:0 default to 00000b. If this register is programmed via EEPROM or another

mechanism, then the value written into this field must be 00000b.

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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