L6918 L6918A

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DIGITAL TO ANALOG CONVERTER (ONLY FOR MASTER DEVICE L6918A)

The built-in digital to analog converter allows the adjustment of the output voltage from 1.100V to 1.850V with

25mV as shown in the previous table 1. The internal reference is trimmed to ensure the precision of ±0.6% and

a zero temperature coefficient around the 70° C. The internal reference voltage for the regulation is programmed

by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is realized by

means of a series of resistors providing a partition of the internal voltage reference. The VID code drives a mul-

tiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier ob-

taining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided for

the VID pins (realized with a 5

µA current generator); in this way, to program a logic "1" it is enough to leave the

pin floating, while to program a logic "0" it is enough to short the pin to GND.

The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the Over/

Under voltage protection (OVP/UVP) thresholds.

The reference for the regulation is generated into the master device and delivered to the slave device through

the VPROG_OUT / VPROG_IN pins.

Programming the "11111" VID code, the device enters the NOCPU state: both devices keeps all mosfets OFF

and the condition is latched. Cycle the power supply to restart operation. Moreover, in this condition, the OVP

protection is still active into the slave device with a 0.8V threshold.

SOFT START AND INHIBIT

At start-up a ramp is generated from the master device increasing its loop reference from 0V to the final value

programmed by VID in 2048 clock periods. The same reference is present on the VPROG_OUT pin, producing

an increasing loop reference also into the slave device. In this way all the devices involved in the multi-phase

conversion start together with the same increasing reference (See Figure 3).

Before soft start, the lower power MOS are turned ON after that VCCDR reaches 2V (independently by Vcc val-

ue) to discharge the output capacitor and to protect the load from high side mosfet failures. Once soft start be-

gins, the reference is increased and also the upper MOS begins to switch: the output voltage starts to increase

with closed loop regulation. At the end of the digital soft start, the Power Good comparator is enabled and the

PGOOD signal is then driven high (See fig. 3). The Under Voltage comparator is enabled when the reference

voltage reaches 0.8V.

The Soft-Start will not take place, if both VCC and VCCDR pins are not above their own turn-on thresholds. The

soft-start takes place, and the Master device starts to increase the reference, only if the SLAVE_OK bus is at

high level. The Slave device keeps this line shorted to GND until it is ready for the start-up while the master

keeps this line free before soft-start; anyway, this line is shorted to GND if VCC and VCCDR are not above the

turn-ON threshold. During normal operation, if any under-voltage is detected on one of the two supplies, the

devices are shutdown.

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