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L6918 数据表(PDF) 21 Page - STMicroelectronics |
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L6918 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 35 page ![]() 21/35 L6918 L6918A MAIN CONTROL LOOP The four phases control loop is composed by two dual phases devices that are independent each other. So, the compensation network and the control loop stability of each device don't depend on the other except for the fact that the other converter represents a load for this one. The L6918/A control loop is composed by the Current Sharing control loop and the Average Current Mode con- trol loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its regulation: the Current Sharing control loop equalize the currents in the inductors while the Average Current Mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 12 reports the block diagram of the main control loop Figure 12. Main Control Loop Diagram CURRENT SHARING (CS) CONTROL LOOP The devices are configured to work in a four synchronized phase application. Since the application is composed by two-phase devices that share reference and synchronization signals, the current sharing between the phases is realized in two different steps: 1. Sharing between the phases of the same device; 2. Sharing between devices. The Current Sharing between phases of the same device uses the internal current information to correct the PWM signal in order to equalize the current. Active current sharing is implemented using the information from Tran conductance differential amplifier in an average current mode control scheme. A current reference equal to the average of the read current (IAVG) is internally built; the error between the read current and this reference is converted to a voltage with a proper gain and it is used to adjust the duty cycle whose dominant value is set by the error amplifier at COMP pin (See fig. 13). The current sharing control is a high bandwidth control allowing current sharing even during load transients. The current sharing error is affected by the choice of external components; choose precise Rg resistor (±1% is necessary) to sense the current. The current sharing error is internally dominated by the voltage mismatch of Tran conductance differential amplifier between phases; considering a voltage mismatch equal to 2mV across the sense resistor, the current reading error is given by the following equation: Where ∆IREAD is the difference between one phase current and the ideal current (IMAX/2). For Rsense=4m Ω and Imax=40A the current sharing error is equal to 2.5%, neglecting errors due to Rg and Rsense mismatches. L1 L2 + + PWM1 1/5 + - 1/5 IINFO2 IINFO1 4/5 ZF(S) PWM2 CO FB COMP RO ERROR AMPLIFIER REFERENCE PROGRAMMED BY VID CURRENT SHARING DUTY CYCLE CORRECTION RFB D02IN1392 ∆I REA D I MAX -------------------- 2mV R SEN SE I MAX ⋅ --------------------------------------- = |
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