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L6918 L6918A

Figure 3. Soft Start

Forcing the master OSC/INH/FAULT pin to a voltage lower than 0.8V, the devices enter in INHIBIT mode: all

the power mosfets are turned off until this condition is removed. When this pin is freed, the OSC/INH/FAULT

pin reaches the band-gap voltage and the soft start begin as previously explained.

In INHIBIT mode the Slave device still have both OVP and UVP protection active referring the thresholds to the

incoming reference present at the VPROG_IN pin if this one is greater than 0.8V. Otherwise (VPROG_IN <

0.8V) UVP is disabled and the OVP threshold is fixed at 0.8V.

DRIVER SECTION

The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the

RDSON), maintaining fast switching transition.

The drivers for the high-side mosfets use BOOT pins for supply and PHASE pins for return. The drivers for the

low-side mosfets use VCCDRV pin for supply and PGND pin for return. A minimum voltage of 5V at VCCDRV

pin is required to start operations of the device. The controller embodies a sophisticated anti-shoot-through sys-

tem to minimize low side body diode conduction time so maintaining good efficiency saving the use of Schottky

diodes. The conduction time is reduced to few nanoseconds assuring that high-side and low-side mosfets are

never switched on simultaneously: when the high-side mosfet turns off, the voltage on its source begins to fall;

when the voltage reaches 2V, the low-side mosfet gate drive is applied with 30ns delay. When the low-side mos-

fet turns off, the voltage at LGATE pin is sensed. When it drops below 1V, the high-side mosfet gate drive is

applied with a delay of 30ns. If the current flowing in the inductor is negative, the source of high-side mosfet will

never drop. To allow the turning on of the low-side mosfet even in this case, a watchdog controller is enabled:

if the source of the high-side mosfet don't drop for more than 240ns, the low side mosfet is switched on so al-

lowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if

the current is negative.

The BOOT and VCCDRV pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND

pin) and power ground (PGND pin) in order to maximize the switching noise immunity.

The peak current is shown for both the upper and the lower driver of the two phases in figure 4.A 10nF capacitive

load has been used.

LS

VPROG_OUT

SLAVE_OK

PGOOD

SYNC_OUT

CH1=PGOOD; CH2=LGATEx; CH3=VPROG_OUT; CH4=SLAVE_OK