L6918 L6918A

24/35

while placing the zero in correspondence with the L-C resonance a simple -20dB/dec shape of the gain is as-

sured (See Figure 15). In fact, considering the usual value for the output filter, the LC resonance results to be

at frequency lower than the above reported zero.

Figure 15. ACM Control Loop Gain Block Diagram (left) and Bode Diagram (right).

Compensation network can be simply designed placing

desired obtaining:

In a four phase operation (since the four phase converter is realized by two dual phase converters in parallel

that shares current using droop), also the other sub-system in parallel must be considered. In particular, in the

above reported relationships, it must be considered with Co and ESR the total output capacitance and equiva-

lent ESR while the output impedance Zo of the other sub-system must be considered in parallel to the output

capacitance Co and to the load Ro.

The output impedance of the other sub-system in parallel results:

LAYOUT GUIDELINES

Since the device manages control functions and high-current drivers, layout is one of the most important things

to consider when designing such high current applications.

A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radi-

ation and a proper connection between signal and power ground can optimize the performance of the control

loops.

Integrated power drivers reduce components count and interconnections between control functions and drivers,

reducing the board space.

Here below are listed the main points to focus on when starting a new layout and rules are suggested for a cor-

rect implementation.

dB

ω

ω

T

ω

Z

ω

LC

K

K

4

5

---

V

IN

V

osc

∆

---------------

1

R

FB

----------

⋅⋅

dB

=

Rout

Cout

ESR

L/2

REF

PWM

d

R

F

R

FB

∆V

OSC

⋅

V

IN

----------------------------------

5

4

---

ω

T

L

2R

DRO OP

ESR

+

()

⋅

-------------------------------------------------------

⋅⋅

⋅

=

C

F

Co

L

2

---

⋅

R

F

--------------------

=

Zo s

()

Z

()

4

5

---

V

IN

∆V

OSC

-------------------

Rsense

Rg

---------------------- Z

()

⋅⋅

⋅

+

1

4

5

---

V

IN

∆V

OS C

-------------------

Z

()

R

FB

---------------

⋅⋅

+

-----------------------------------------------------------------------------------------------

=