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Droop function is provided only for positive load; if negative load is applied, and then IINFOx<0, no current is

sunk from the FB pin. The device regulates at the voltage programmed by the VID.

OUTPUT VOLTAGE MONITORING AND PROTECTION: POWER GOOD

The output voltage is monitored by the Slave device through the pin VSEN. If it is not within +12/-10% (typ.) of

the programmed value, the PGOOD output is forced low. PGOOD is always active in the Slave device, also dur-

ing soft-start. PGOOD in the Master device has the only masking function during soft-start. Since the master

has not the output voltage sense, it keeps the PGOOD to GND during soft-start and after this step it is freed.

The Slave device provides Over-Voltage protection: when the voltage sensed by VSEN reaches 117% (typ.) of

the reference voltage present at the VPROG_IN pin, the Slave device stops switching keeping the LS mosfets

ON. The FAULT pin is driven high (5V) and the SLAVE_OK line is pulled low. The master device then stops

switching keeping the LS mosfets ON, too. Since the condition is latched, power supply (Vcc) turn off and on is

required to restart operations.

Under voltage protection is also provided and still detected by the Slave device. If the output voltage drops be-

low the 60% (typ.) of the reference voltage present at the VPROG_IN pin for more than one clock period, the

Slave device stops switching turning OFF all mosfets and pulling down the SLAVE_OK line: the Master device

stops switching with LS mosfets ON. The OSC/INH/FAULT is not driven high in this case.

Both Over Voltage and Under Voltage are active also during soft start (Under Voltage after than Vout reaches

0.8V). During soft-start the reference voltage used to determine the UV threshold is the increasing voltage driv-

en by the 2048 soft start digital counter. Moreover, OVP is always active, even during INHIBIT (see relevant

section).

Over / Under Voltage behavior are shown in Figure 9.

Figure 9. OVP and UVP latch

REMOTE VOLTAGE SENSE

A remote sense buffer is integrated into the device to allow output voltage remote sense implementation without

any additional external components. In this way, the output voltage programmed is regulated between the re-

mote buffer inputs compensating motherboard trace losses or connector losses if the device is used for a VRM

module.

The very low offset amplifier senses the output voltage remotely through the pins FBR and FBG (FBR is for the

regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN pin with

unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and guarded by a power plane re-

sults in common mode coupling for any picked-up noise.

If remote sense is not required, the output voltage is sensed by the VSEN pin connecting it directly to the output

voltage. In this case the FBG and FBR pins must be connected anyway to the regulated voltage

LS

OSC

SLAVE_OK

LS

OSC

SLAVE_OK

UNDER VOLTAGE LATCH

OVER VOLTAGE LATCH

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L6918A

L6918A

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