27/35

L6918 L6918A

Figure 18. PCB layout connections for sense nets.

Interconnections between devices.

Master and Slave devices share reference and other signals for the regulation. To avoid noise injection into de-

vices, it is recommended to route these nets carefully.

– VPROG_IN / VPROG_OUT: This is the reference for the regulation. It must be routed far away from

any noisy trace and guarded by ground traces in order to avoid noise injection into the device. It can

be filtered with a 30nF maximum of distributed capacitance vs. signal ground.

– SLAVE_OK: This signal is used by the devices for the start-up synchronization and also to commu-

nicate UVP from Slave to Master device. It must be filtered by 1nF capacitor near the pin of each de-

vice to avoid the noise to cause false protection's trigger.

Demo Board Description

The L6918 demo board shows the operation of the device in a four phases application. This evaluation board al-

lows output voltage adjustability (1.100V - 1.850V) through the switches S0-S4 and high output current capability.

to give maximum flexibility in the mosfet choice.

The four layers demo board's copper thickness is of 70

µm in order to minimize conduction losses considering

the high current that the circuit is able to deliver.

Demo board schematic circuit is reported in Figure 19.

Several jumpers allow setting different configurations for the device: JP3, JP4 and JP5 allow configuring the

remote buffer as desired. Simply shorting JP4 and JP5 the remote buffer is enabled and it senses the output

voltage on-board; to implement a real remote sense, leave these jumpers open and connect the FBG and FBR

connectors on the demo board to the remote load. To avoid using the remote buffer, simply short all the jumpers

JP3, JP4 and JP5. Local sense through the R7 is used for the regulation.

The input can be configured in different ways using the jumpers JP1, JP2 and JP6; these jumpers control also

(See Figure 20).

NOT CORRECT

CORRECT

To PHASE

connection

VIA to GND plane

To HS Gate

and Source

To LS Drain

and Source

Wrong (left) and correct (right) connections for the current reading sensing nets.