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STM32F427AI 数据表(PDF) 147 Page - STMicroelectronics |
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STM32F427AI 数据表(HTML) 147 Page - STMicroelectronics |
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147 / 240 page ![]() DS9405 Rev 12 147/240 STM32F427xx STM32F429xx Electrical characteristics 197 Note: Refer to the I2S section of the RM0090 reference manual for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition. tv(WS) WS valid time Master mode 0 6 ns th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 1 - th(WS) WS hold time Slave mode 0 - tsu(SD_MR) Data input setup time Master receiver 7.5 - tsu(SD_SR) Slave receiver 2 - th(SD_MR) Data input hold time Master receiver 0 - th(SD_SR) Slave receiver 0 - tv(SD_ST) th(SD_ST) Data output valid time Slave transmitter (after enable edge) - 27 tv(SD_MT) Master transmitter (after enable edge) - 20 th(SD_MT) Data output hold time Master transmitter (after enable edge) 2.5 - 1. Evaluated by characterization. 2. The maximum value of 256xFs is 45 MHz (APB1 maximum frequency). Table 64. I2S dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Max Unit |
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