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STM32F427AI 数据表(PDF) 181 Page - STMicroelectronics |
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STM32F427AI 数据表(HTML) 181 Page - STMicroelectronics |
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181 / 240 page ![]() DS9405 Rev 12 181/240 STM32F427xx STM32F429xx Electrical characteristics 197 Figure 62. Synchronous non-multiplexed PSRAM write timings th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 0 - ns t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 - - th(CLKH- NWAIT) FMC_NWAIT valid after FMC_CLK high 0 - - 1. CL = 30 pF. 2. Guaranteed by characterization results. Table 98. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max Unit t(CLK) FMC_CLK period 2THCLK − 1 - ns td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 0.5 ns t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK -ns td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0 ns td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - ns td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0 ns Table 97. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter Min Max Unit MS32760V1 FMC_CLK FMC_NEx FMC_A[25:0] FMC_NWE FMC_D[15:0] D1 D2 FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 td(CLKL-NExL) td(CLKH-NExH) td(CLKL-AV) td(CLKH-AIV) td(CLKH-NWEH) td(CLKL-NWEL) td(CLKL-Data) tsu(NWAITV-CLKH) th(CLKH-NWAITV) FMC_NADV td(CLKL-NADVL) td(CLKL-NADVH) td(CLKL-Data) FMC_NBL td(CLKH-NBLH) |
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