SERCON410B datasheet(10/34 Pages) STMICROELECTRONICS

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2 PIN DESCRIPTION

Signal (s)

Pin (s)

Function

D15-0

77-80,

82-85,

87-90,

92-95

I/O

Data bus: for 8-bit-wide bus interfaces, data is written to and read via D7-0,

for 16-bit-wide bus interfaces via D15-0. When ADMUX is 1, the address

which is stored in the address latch with ALEL and ALEH is input via D15-0.

A15-0

56-59,

61-64,

66-69,

71-74

I/O

Address bus: when ADMUX is 0 the pins are inputs, when ADMUX is 1, they

are outputs for the address stored with ALEL (A7-0) and ALEH (A15-8). In

the 8-bit bus mode, A0 distinguishes which byte is transmitted via

D7-0 (depends on BYTEDIR). In the 16-bit bus mode, data is tansferred via

D7-0 only when A0 is 0. A10-1 selects the words of the internal RAM; A6-

1the control registers.

ALEL, ALEH

54, 53

Address latch enable, low and high, active high: they are only used when

ADMUX is 1. When ALEL/ALEH is 1, the signals go from the data bus to

the address bus, when ALEL/ALEH = 0, they store the address. When

ADMUX is 0, ALEL/ALEH have to be connected to VDD.

RDN

Read: for the Intel bus interface, data is read when RDN is 0. For the

Motorola bus interface, data is read or written to when RDN is 0

(BUSMODE1 = 0) or RDN is 1 (BUSMODE1 = 1).

WRN

Write: for the Intel bus interface, data is written to when WRN is 0. For the

Motorola bus interface, WRN selects read (WRN = 1) and write (WRN = 0)

operations of the data bus.

BHEN

Byte high enable, active low: in the 16-bit bus mode, data is transferred via

D15-8 when BHEN is 0.

MCSN0,

MCSN1

46,47

Memory chip select, active low: to access the internal RAM MCSN0 and

MCSN1 must be 0.

PCSN0,

PCS1

48,49

Periphery chip select, active low (PCSN0) and active high (PCSN1): to

access the control registers PCSN0 must equal 0 and PCS1 must equal 1.

BUSYN

RAM busy, active low: becomes active if an access to an address of the

dual port RAM is performed simultaneously to an access to the same

memory location by the internal telegram processing.

DMAREQR

DMA request receive, active high: becomes active if data from the receive

FIFO can be read. At the beginning of the read operation of the last word of

the receive FIFO, DMAREQR becomes inactive.

DMAACKRN

DMA acknowledge receive, active low: when DMAACKRN is 0, the receive

FIFO is read, independent of the levels on A6-1 and the chip select signals.

DMAREQT

DMA request transmit, active high: becomes active when data can be

written to the transmit FIFO. DMAREQT becomes inactive again at the

beginning of the last write access to the transmit FIFO.

DMAREQTN

DMA acknowledge transmit, active low: when DMAACKTN is 0, the

transmit FIFO is written to when there is a bus write access independent of

the levels on A6-1 and the chip select signals.

ADMUX

Address data bus: when ADMUX is 0 A15-0 are the address inputs, when

ADMUX is 1 A15-0 are the outputs of the address latch.

BUSMODE0,

BUSMODE1

97,98

Bus mode: BUSMODE0 = 0 turns on the Intel bus interface (RDN = read,

WRN = write), BUSMODE0 = 1 selects the Motorola interface (RDN = data

strobe, WRN = read/write). BUSMODE1 selects the 0-active data strobe

(BUSMODE1 = 0) or the 1-active data strobe (BUSMODE1 = 1).

BUSWIDTH

Bus width: selects the 8-bit- (0) or the 16-bit-wide interface (1).

Table 1. SERCON410B I/O Port Function Summary

SERCON410B

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