SERCON410B datasheet(12/34 Pages) STMICROELECTRONICS

12 / 34 page

Signal (s)

Pin (s)

Function

SCLKO2

Clock output: outputs the SCLK clock divided by 2.

SCLKO4

Clock output: outputs the SCLK clock divided by 4.

MCLK

Master clock for telegram processing and timing control, frequency 12 to 20

MHz.

RSTN

Reset, active low. Must be zero for at least 50 ns after power on.

TEST

Test, active high. Has to be tied to VSS.

OUTZ

Puts outputs into high impedance state, active high: OUTZ is 1 puts all pins

into a high impedance state. The clocks are turned off and the circuit is

reset. For the in-circuit test and for turning on the powerdown mode.

NDTRO

NAND tree output. For the test at the semiconductor manufacturers and for

the connection test after board production. NDTRO is not set to a high

impedance state.

VSS

3,15,23,

33,42,

50,60,

70,81,

Ground pins.

VDD

1,8,19,

27,37,

55,65,

76,86

Power supply +5 V

± 5%.

Table 1. SERCON410B I/O Port Function Summary (Continued)

PIN DESCRIPTION (Continued)

SERCON410B

8/30

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