ST10C167 datasheet(11/65 Pages) STMICROELECTRONICS

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ST10C167

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IV - MEMORY ORGANIZATION

The

memory

space

the

ST10C167

configured in a Von-Neumann architecture. Code

memory, data memory, registers and I/O ports are

organized within the same linear address space of

16M Byte.

The entire memory space can be accessed Byte-

wise or Wordwise. Particular portions of the

on-chip memory have additionally been made

directly bit addressable.

ROM : 32K Byte of on-chip ROM.

RAM

2K Byte

on-chip

internal

RAM

(dual-port) is provided as a storage for data, sys-

tem stack, general purpose register banks and

code. The register bank can consist of up to 16

wordwide (R0 to R15) and/or Bytewide (RL0,

RH0,

…, RL7, RH7) general purpose registers.

XRAM : 2K Byte of on-chip extension RAM (sin-

gle port XRAM) is provided as a storage for data,

user stack and code.

The XRAM is connected to the internal XBUS and

is accessed like an external memory in 16-bit

demultiplexed bus-mode without waitstate or

read/write delay (80ns access at 25MHz CPU

clock). Byte and Word access is allowed.

The

XRAM

address

range

00’E000h

00’E7FFh if the XRAM is enabled (XPEN bit 2 of

SYSCON register). As the XRAM appears like

external memory, it cannot be used for the

ST10C167’s system stack or register banks. The

XRAM is not provided for single bit storage and

therefore is not bit addressable. If bit XRAMEN is

cleared, then any access in the address range

00’E000h - 00’E7FFh will be directed to external

memory interface, using the BUSCONx register

corresponding to address matching ADDRSELx

SFR/ESFR : 1024 Byte (2 * 512 Byte) of address

space is reserved for the special function register

areas. SFRs are wordwide registers which are

used for controlling and monitoring functions of

the different on-chip units.

CAN : Address range 00’EF00h - 00’EFFFh is

reserved for the CAN Module access. The CAN is

enabled by setting XPEN bit 2 of the SYSCON

tiplexed addresses and a 16-bit data bus (Byte

accesses are possible). Two wait states give an

access time of 160ns at 25MHz CPU clock. No

tristate waitstate is used.

Note

If the CAN module is used, Port 4 can not

be programmed to output all 8 segment

address lines. Thus, only 4 segment

address lines can be used, reducing the

external memory space to 5M Byte (1M

Byte per CS line).

In order to meet the needs of designs where more

memory is required than is provided on chip, up to

16M Byte of external RAM and/or ROM can be

connected to the microcontroller.

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