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ST10C167 数据表(PDF) 47 Page - STMicroelectronics |
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ST10C167 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 65 page ![]() ST10C167 47/65 Note 1. Guaranteed by design characterization. t48 CC RdCS, WrCS Low Time (with RW delay) 30 + tC – 2TCL - 10 + tC –ns t49 CC RdCS, WrCS Low Time (no RW delay) 50 + tC – 3TCL - 10 + tC –ns t50 CC Data valid to WrCS 26 + tC – 2TCL - 14+ tC –ns t51 SR Data hold after RdCS 0 – 0 – ns t52 1 SR Data float after RdCS – 20 + tF – 2TCL - 20 + tF ns t54 CC Address hold after RdCS, WrCS 20 + tF –2TCL - 20 + tF –ns t56 CC Data hold after WrCS 20 + tF –2TCL - 20 + tF –ns Table 18 : Multiplexed bus characteristics (continued) Symbol Parameter Max. CPU Clock = 25MHz Variable CPU Clock 1/2TCL = 1 to 25MHz Unit Min. Max. Min. Max. XX - ELECTRICAL CHARACTERISTICS (continued) |
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