ST10C167 datasheet(61/65 Pages) STMICROELECTRONICS

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ST10C167

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XX - ELECTRICAL CHARACTERISTICS (continued)

Notes 1. This is the last opportunity for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence

is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10C167 requesting the bus.

2. The next ST10C167 driven bus cycle may start here.

XX.4.13 - High-speed synchronous serial interface (SSC) timing

Master mode

VCC =5V ±10%, VSS = 0V, CPU clock = 25MHz, TA = -40 to +125°C, CL = 100pF

Note

1. timi ng guaranteed by design.

Figure 24 : External bus arbitration, (regaining the bus)

Symbol

Parameter

Max. Baud rate = 6.25M Baud

(<SSCBR> = 0001h)

Variable Baud rate

(<SSCBR>=0001h-FFFFh)

Unit

Min.

Max.

Min.

Max.

t300

SSC clock cycle time

160

8 TCL

262144 TCL

t301

SSC clock high time

–

t300/2 - 10

–ns

t302

SSC clock low time

–

t300/2 - 10

–ns

t303

SSC clock rise time

–

t304

SSC clock fall time

–

t305

Write data valid after shift edge

–

t306

Write data hold after shift edge

-2

–

-2

–

t307p SR Read data setup time before

latch edge, phase error

detection on (SSCPEN = 1)

–

2TCL+20

–

t308p SR Read data hold time after latch

edge, phase error detection on

(SSCPEN = 1)

4TCL

–

4TCL

–

t307

Read data setup time before

latch edge, phase error

detection off (SSCPEN = 0)

–

t308

Read data hold time after latch

edge, phase error detection off

(SSCPEN = 0)

0–

–

CLKOUT

HOLD

HLDA

Other

Signals

CSx

(On P6.x)

BREQ

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