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ST20C2 数据表(PDF) 67 Page - STMicroelectronics |
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ST20C2 数据表(HTML) 67 Page - STMicroelectronics |
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67 / 212 page  devsb 67/212 ® devsb device store byte Code: 2F F1 Description: Perform a device write from memory, a memory-mapped device or a peripheral. Store the least significant byte of Breg into the byte addressed by Areg. The memory access performed by this instruction is guaranteed to be correctly sequenced with respect to other device-access instructions. Also the instruction is guaranteed to be executed after all normal memory store instructions that appear before it in the code sequence, and before all normal memory stores that appear after it. Definition: if (PeripheralStart ≤ Areg ≤ PeripheralEnd) PeripheralByte ′[Areg] ← Breg 0..7 else byte ′[Areg] ← Breg 0..7 Areg ′← Creg Breg ′← undefined Creg ′← undefined Error signals: none Comments: Secondary instruction. See also: devlb devss devsw sb |
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