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ST20C2 数据表(PDF) 20 Page - STMicroelectronics |
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ST20C2 数据表(HTML) 20 Page - STMicroelectronics |
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20 / 212 page ![]() ® 20/212 3 Registers 3.1 Machine registers This section introduces the ST20 processor registers that are visible to the programmer. Firstly the set of registers known as state registers are presented and discussed. These fully define the state of the executing process. Secondly the other registers of interest to the programmer, are presented. 3.1.1 Process state registers The state of a executing process at any instant is defined b y the contents of the machine registers listed in Table 3.1. The ‘register’ column gives the abbreviated name of the register. The ‘full name / description’ column provides the full textual name which is usually used when referencing a register in this manual; and where unclear, a brief description of the information contained in this register. In addition there is a small number of registers used to implement block moves. Status register The Status register contains status bits which describe the current state of the process and any errors which may have occurred. The contents of the Status register are shown in Table 3.2. ‘Shadow’ registers When a high priority process interrupts a low priority process, the state of the currently executing process needs to be saved. For this purpose, two sets of process state registers are provided, one each for high and low priority. On interrupt, the processor switches to using the high priority registers, leaving the low priority registers to preserve the low priority state. A high priority process may manipulate the low priority ‘shadow’ registers with the instructions ldshadow and stshadow. In the definitions of these instructions, the process state registers have a subscript (e.g. Areg[LowPriority]) indicating the priority. register full name / description process modes Status status register Wptr workspace pointer - contains the address of the workspace of the currently execut- ing process Iptr instruction pointer register - pointer to next instruction to be executed Areg integer stack register A Breg integer stack register B Creg integer stack register C Table 3.1 Process state registers |
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