ST20C2 datasheet(28/212 Pages) STMICROELECTRONICS

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the word-length of the processor.

• Thirdly, it enables any number of secondary instructions to be implemented.

The following provides some simple examples of encoding:

• The instruction ldc 17 is encoded with the sequence:

pfix 1; ldc 1

• The instruction add is encoded by:

opr 5

• The instruction and is encoded by:

opr 70

which is in turn encoded with the sequence:

pfix 4; opr 6

To aid clarity and brevity, prefix sequences and the use of

opr are not explicitly shown

in this guide. Each instruction is represented by a mnemonic, and for primary

instructions an item of data, which stands for the appropriate instruction component

sequence. Hence in the above examples, these are just shown as:

ldc 17, add, and

and. (Also, where appropriate, an expression may be placed in a code sequence to

represent the code needed to evaluate that expression.

4.2

Generating prefix sequences

Prefixing is intended to be performed by a compiler or assembler. Prefixing b y hand is

not advised.

Normally a value can be loaded into the instruction data value by a variety of different

prefix sequences . It is important to use the shortest possible sequence as this

enhances both code compaction and execution speed. The best method of optimizing

object code so as to minimize the number of prefix instructions needed is shown

below.

4.2.1

Prefixing a constant

The algorithm to generate a constant instruction data value

e for a function op is

described by the following recursive function.

prefix( op , e ) = IF

< 16 AND e 0

op( e )

prefix( pfix, e >> 4 ); op( e

∧ #F)

< 0

prefix( nfix, (~e) >> 4 ); op( e

∧ #F )

where

( op, e ) is the instruction component with function code op and data field

e, ~ is a bitwise NOT, and >> is a logical right shift.

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